A level shifter is commonly used in a circuitry for shifting voltage levels.
Please refer to FIG. 1, which is a functional block diagram illustrating a conventional level shifter 10. The level shifter 10 includes an input buffer 102, an output buffer 106 and a level adjusting unit 104. The input buffer 102 is biased between a first voltage source (VDD) and a ground source (GND) for receiving an input signal Vin so that the input signal Vin has a voltage level ranged between the voltage level of the first voltage source and the voltage level of the ground source. The output buffer 106 is biased between a second voltage source (VPP) and the ground source for outputting an output signal Vout so that the output signal Vout has a voltage level ranged between the voltage level of the second voltage source and the voltage level of the ground source (GND). The level adjusting unit 104 is electrically coupled between the input buffer 102 and the output buffer 106, and biased between the second voltage source and the ground source for shifting the voltage level of the input signal Vin, which is primarily ranged VDD˜GND, so as to generate the output signal Vout with the desired level ranged VPP˜GND, wherein VPP is greater than VDD. In brief, after the input buffer 102 receives and transmits the input signal Vin to the level adjusting unit 104, the voltage level of the input signal Vin is adjusted from a level ranged VDD˜GND to a level ranged VPP˜GND, which is then outputted by the output buffer 106 as the output signal Vout.
In the above-mentioned circuit system, the first voltage source and the second voltage source are independent from each other. Therefore, the first voltage source and the second voltage source could be actuated asynchronously. If the second voltage source has been actuated but the first voltage source has not yet, the input buffer 102 relying on the voltage level of the first voltage source for work cannot function normally. Meanwhile, the voltage at the output end of the input buffer 102 would be indefinite and thus adversely affect the operation of the downstream output buffer 106. Accordingly, the overall output of the level shifter 10 would become abnormal.